EECS 427 - Very Large Scale Integrated Design I
Section: 001
Term: FA 2007
Subject: Electrical Engineering and Computer Science (EECS)
Department: CoE Electrical Engineering and Computer Science
Requirements & Distribution:
Enforced Prerequisites:
EECS 270 and 312 with a grade of at least C; or graduate standing.
Other Course Info:
F, W.
This course counts toward the 60 credits of math/science required for a Bachelor of Science degree.
May not be repeated for credit.
Primary Instructor:

Objectives: This course introduces mask-level integrated circuit design.

Correct engineering design methodology is emphasized. Topics covered in lectures include: CMOS processes, mask layout methods and design rules; circuit characterization and performance estimation; design for testability; and CMOS subsystem and system design.

Prerequisites: EECS 270 and 312. Students are expected to know logic design, transistor-level circuit design (especially static CMOS), and device physics. Some background in computer architecture is helpful (EECS 370/470), but not required.

The term project involves the design of a 16-bit RISC microprocessor. The initial cell designs probably will not be used in the final project and must be done individually. You are encouraged to interact with others, but until you are asked to form teams, the work on your cell designs, simulations, etc., must be your own. There is an initial homework assignment to ensure that all students have the prerequisite digital IC design knowledge to succeed in EECS 427. The final project will be done in teams of four. The project must be completed, and you must submit a final report in the format specified. Within the constraints of available funding, eligible projects will be fabricated through the MOSIS service. If your project is fabricated, it must be tested; you can get credit for testing it in EECS 579 or as a directed study project. You are encouraged to enter your design in the DAC Student Design Contest.

There will be ~60 minute quizzes approximately every 4 weeks (3 total) during the semester.

Required text:
Jan Rabaey, Anantha Chandrakasan, and Borivoje Nikolic, Digital Integrated Circuits: A Design Perspective, second edition, Prentice Hall, 2003.

We will also be pulling material from the following texts:
N. Weste and D. Harris, CMOS VLSI Design: A Circuits and Systems Perspective, 3rd edition, Addison-Wesley, 2005.
Design of High-Performance Microprocessor Circuits, edited by A. Chandrakasan, W. Bowhill, and F. Fox, IEEE Press, 2001.

Another useful circuit design reference is:
D.A. Hodges, H.G. Jackson, and R.A. Saleh, Analysis and Design of Digital Integrated Circuits in Deep Submicron Technology, 3rd edition, McGraw Hill, 2004.

Grading scheme:
Homeworks (including project presentation): 10%
CAD assignments: 35%
Quizzes: 24% (8% each)Final project, report, and individual contributions: 31%

EECS 427 - Very Large Scale Integrated Design I
Schedule Listing
001 (LEC)
TuTh 10:00AM - 11:30AM
011 (DIS)
Tu 5:30PM - 6:30PM
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