EECS 478 - Logic Circuit Synthesis and Optimization
Section: 001
Term: FA 2017
Subject: Electrical Engineering and Computer Science (EECS)
Department: CoE Electrical Engineering and Computer Science
Credits:
4
Requirements & Distribution:
BS
Enforced Prerequisites:
EECS 270 and 203 with a grade of at least C; and senior or graduate standing.
Other Course Info:
F, W.
BS:
This course counts toward the 60 credits of math/science required for a Bachelor of Science degree.
Repeatability:
May not be repeated for credit.
Primary Instructor:

Advanced design of logic circuits. Technology constraints. Theoretical foundations. Computer-aided design algorithms. Two-level and multilevel optimization of combinational circuits. Optimization of finite-state machines. High-level synthesis techniques: modeling, scheduling, and binding. Verification and testing.

EECS 478 - Logic Circuit Synthesis and Optimization
Schedule Listing
001 (LEC)
 
32259
Open
27
 
-
TuTh 12:00PM - 1:30PM
011 (DIS)
P
32260
Open
27
 
-
F 11:30AM - 12:30PM
NOTE: Data maintained by department in Wolverine Access. If no textbooks are listed below, check with the department.


ISBN: 0387310045
Logic synthesis and verification algorithms, Author: by Gary D. Hachtel; Fabio Somenzi., Publisher: Springer 1st softco 2006
Optional
ISBN: 9780521857482
Switching and finite automata theory, Author: Zvi Kohavi, Niraj K. Jha., Publisher: Cambridge University Press 3rd ed. 2010
Optional
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