EECS 478 - Logic Circuit Synthesis and Optimization
Section: 001
Term: WN 2018
Subject: Electrical Engineering and Computer Science (EECS)
Department: CoE Electrical Engineering and Computer Science
Credits:
4
Requirements & Distribution:
BS
Enforced Prerequisites:
EECS 270 and 203 with a grade of at least C; and senior or graduate standing.
Other Course Info:
F, W.
BS:
This course counts toward the 60 credits of math/science required for a Bachelor of Science degree.
Repeatability:
May not be repeated for credit.
Primary Instructor:

Advanced design of logic circuits. Technology constraints. Theoretical foundations. Computer-aided design algorithms. Two-level and multilevel optimization of combinational circuits. Optimization of finite-state machines. High-level synthesis techniques: modeling, scheduling, and binding. Verification and testing.

EECS 478 - Logic Circuit Synthesis and Optimization
Schedule Listing
001 (LEC)
 
25548
Open
62
 
-
TuTh 9:00AM - 10:30AM
011 (DIS)
P
25549
Open
62
 
-
F 11:30AM - 12:30PM
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