EECS 527 - Layout Synthesis and Optimization
Section: 001
Term: WN 2018
Subject: Electrical Engineering and Computer Science (EECS)
Department: CoE Electrical Engineering and Computer Science
Credits:
3
Requirements & Distribution:
BS
Waitlist Capacity:
unlimited
Advisory Prerequisites:
EECS 281 or EECS 478 or Graduate Standing.
Other Course Info:
W.
BS:
This course counts toward the 60 credits of math/science required for a Bachelor of Science degree.
Repeatability:
May not be repeated for credit.
Primary Instructor:

Theory of circuit partitioning, floor planning and placement algorithms. Techniques for routing and clock tree design. Timing analysis and cycles time optimization. Topics in low-power design. Large-scale optimization heuristics, simulated annealing and Al techniques in CAD. Modern physical design methodologies and CAD software development.

EECS 527 - Layout Synthesis and Optimization
Schedule Listing
001 (LEC)
P
32219
Open
10
 
-
MW 3:00PM - 4:30PM
Note: 3 Credit hours: Register for Lec 001
002 (LEC)
 
32220
Open
10
 
-
MW 3:00PM - 4:30PM
Note: 4 Credit hours: Register for Lec 002 and Dis 021. STUDENTS ELECTING DIS 021 WILL BE AUTO-ENROLLED IN LECTURE 002.
021 (DIS)
P
32221
Open
5
 
-
M 4:30PM - 5:30PM
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